Intel IPU
Intel IPU E2100
Production engineering on Intel Infrastructure Processing Unit with IPDK and IDPF integration.
- IPDK development
- P4 pipeline programming
- IDPF host interface
- OPI integration
Service · Infrastructure Offload
IPU & DPU Engineering Services
Hands-on engineering expertise in Intel IPU and Marvell DPU platforms - from network function offloading and P4 programming to DPDK data plane acceleration and bare-metal provisioning at cloud scale.
2+IPU / DPU platforms
NFsOffloaded to DPU
P4+Data plane expertise
IPU / DPU - Infrastructure Offload Architecture
Our Capabilities
What we bring to your IPU & DPU project
PalC has hands-on engineering experience with Intel IPU (E2100) and Marvell OCTEON DPU platforms - from bringup and NF offloading to production deployment at cloud infrastructure scale.
Marvell DPU
Marvell OCTEON DPU
Deep engineering on OCTEON DPU family with ARM-native dataplane and DPDK acceleration.
- OCTEON SDK and DPDK
- ARM Neoverse dataplane
- ODP integration
- Hardware accelerator integration
NF Offload
Network Function Offloading
End-to-end offloading from host CPU to IPU/DPU dataplane for vSwitch, vRouter, ACL and IPSec.
- OVS / vSwitch offload
- vRouter offload
- ACL / firewall offload
- IPSec / TLS offload
Deep Dive
Proven engineering across both platforms
# IPDK P4 program packet forwarding
$ p4c --target dpdk --arch pna ...
[INFO] P4Runtime server started :9559
[INFO] GNMI server started :9339
$ p4c --target dpdk --arch pna ...
[INFO] P4Runtime server started :9559
[INFO] GNMI server started :9339
Intel IPU E2100
P4-programmable pipeline on Intel IPU
- P4 program development using PNA
- IPDK integration with infrap4d
- IDPF host interface and virtio
- OPI framework integration
- Linux SF and SR-IOV configuration
Marvell OCTEON DPU
ARM-native data plane on Marvell OCTEON
- DPDK application development
- ODP framework integration
- Hardware crypto/compression
- Marvell SDK/BSP bringup
- Host CPU to DPU communication
# DPDK app on Marvell OCTEON DPU
EAL: Detected 16 ARM Neoverse cores
PMD: octeontx2_net port 0 ready
Host CPU offloaded: 94%
EAL: Detected 16 ARM Neoverse cores
PMD: octeontx2_net port 0 ready
Host CPU offloaded: 94%
Before: vSwitch, IPSec, ACL/NAT on host CPU
After: vSwitch, IPSec HW offload, ACL in DPU pipeline
After: vSwitch, IPSec HW offload, ACL in DPU pipeline
NF Offloading
Offloading network functions from host to DPU
- OVS/vSwitch hardware flow table offload
- IPSec termination on DPU crypto
- Stateful firewall and ACL enforcement
- SR-IOV and virtio emulation
- Control-plane integration with EVPN/BGP
Architecture
The DPU / IPU engineering stack
DPU and IPU engineering spans multiple layers - from hardware bringup and firmware through data plane programming and NF deployment up to orchestration and cloud integration.
Application LayerVMs, containers, cloud workloads on host
NF Offload LayervSwitch, FW, IPSec, NAT on DPU/IPU
DPU / IPU PlatformARM cores, P4 pipeline, HW accelerators
Infrastructure & FabricPCIe, network fabric, bare-metal provisioning
Selected Layer
Application Layer
Application and orchestration workloads that drive network and infrastructure demand on host systems.
- Kubernetes/OpenStack orchestration
- VM and container workload lifecycle
- SDN controller policy integration
- Cloud API driven provisioning
Application & Orchestration Layer
Kubernetes / OpenStackVM / Container WorkloadsSDN ControllerCloud APIs
Network Function Offload
OVS / vSwitch OffloadIPSec / TLS TerminationACL / Stateful FirewallNAT / Load BalancerRDMA / RoCE
DPU / IPU Platform
Intel IPU E2100 (IPDK / P4)Marvell OCTEON (DPDK / ODP)ARM Neoverse CoresHW Crypto / CompressP4-Programmable PipelineSR-IOV / virtio
Infrastructure & Fabric
PCIe / CXL Host Interface25G / 100G Network UplinkBare-metal ProvisioningOut-of-band Management
Use Cases
Where PalC delivers IPU & DPU engineering
From cloud provider infrastructure to enterprise data centres, DPU and IPU offloading unlocks host CPU efficiency, consistent network policy, and hardware-accelerated security at scale.
Cloud Infrastructure Offload
Offload virtualized network infrastructure from host CPUs to IPU/DPU.
Hardware-accelerated IPSec
Move IPSec tunnel termination and TLS offload to DPU hardware crypto.
Stateful Firewall & ACL Offload
Implement microsegmentation and firewall policy in DPU/IPU dataplane.
Bare-metal Cloud Networking
Enable cloud-like network policy on bare-metal tenants with DPU/IPU edge.
RDMA & Storage Acceleration
Accelerate RoCE and storage traffic while reducing host CPU involvement.
Telco / NFV Acceleration
Run UPF/BNG/CGN/DPI with DPU acceleration for telco-grade performance.
Work With Us
Bring IPU & DPU expertise to your project
Whether you're evaluating Intel IPU or Marvell DPU platforms, building a proof of concept, or deploying at production scale - PalC engineers can accelerate your delivery.
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Platform bringup & SDK integration
Intel IPDK, Marvell OCTEON SDK, DPDK.
⚡
NF offload design & implementation
End-to-end offloading with performance validation.
✓
Performance benchmarking & tuning
Systematic profiling to hit throughput and latency targets.
👥
Knowledge transfer & team enablement
Hands-on training and documentation for sustained ownership.
Talk to an IPU / DPU Expert
Share your offload, acceleration, or platform goals. Our engineering team will review your use case and map a practical delivery plan.
Architecture and readiness review for Intel IPU / Marvell DPU
Target offload candidates identified with measurable ROI
Execution plan from PoC to production rollout
Proven outcomes from the field
Deployments across AI fabrics, multi-cloud, automation, and security.
ODM PARTNERS
TRUSTED BY LEADING TECHNOLOGY PARTNERS
Next steps
Bring networking expertise to your project
Whether designing a new BGP fabric, migrating to Segment Routing, or hardening routing security, PalC engineers can accelerate your delivery.
